FIG. 1 shows a line card or a circuit board according to the prior art for incorporation into a switchgear cabinet. The line card is rectangular and has a plurality of edges. In this case, a plug for plugging the line card into the switchgear cabinet is provided at the rear side of the line card, the line card being able to be connected to an internal bus of the switch-gear cabinet via the plug.
An integrated circuit for high-speed data processing is provided on the circuit board and, in the example shown, is connected to the plug via the input side via two parallel buses A, B. The buses A, B each comprise a plurality of bus lines running parallel. The integrated circuit carries out a data processing of the incoming data and outputs then, in the example illustrated in FIG. 1, via two buses C, D in each case to parallel-serial converters connected downstream. The parallel-serial converters carry out a parallel-serial conversion of the data present in parallel on the bus lines. The parallel-serial converters output a serial data stream via serial data outputs A via connected lines. By way of example, the data arriving from the bus A are processed on the integrated circuit and the data are then applied via the bus C to the parallel-serial converter connected downstream. The latter then outputs a serial data stream via the output port A.
FIG. 2 shows the arrangement of the bus lines in the case of a conventional circuit board according to the prior art. The bus lines are arranged in a preferred direction proceeding from the plug toward the end side of the line card within the switchgear cabinet. The integrated circuit of the data processing is arranged in a housing having a plurality of sides. In the case of the example illustrated in FIG. 2, the housing has four sides, a parallel interface being provided at each side of the housing. Each of said parallel interfaces comprises a plurality of data inputs and outputs. In the case of the example illustrated in FIG. 2, the high-speed IC has four parallel interfaces each arranged at a side of the housing. The parallel interfaces serve for connecting the integrated circuit to the bus lines for the data exchange. Many applications require data transmission rates in the GHz range, i.e. the data are transmitted via the data bus with a data transmission speed of a few gigabits per second. Electrical signals on printed circuit boards or circuit boards propagate more slowly than light. The speed of light of 300 000 km per second applies to a propagation of the light in a vacuum or to an approximation also in air. The actual propagation speed of an electrical signal is proportional to the root of the relative electrical constant Er. If the relative electrical constant is Er=10, for example, the propagation speed of the electrical signal is about 100 000 km per second. The electrical signals propagate on a circuit board in the lines with a finite propagation speed which depends greatly on the printed circuit board material. The second influencing factor for the signal propagation time is the length of the conductor tracks. The longer the conductor track to which the high-frequency signal is applied, the longer the time required by the signal to pass from a transmitting device to a receiving device. If a plurality of signals are transmitted simultaneously, for example via a data bus, then the signals will arrive at the receiving device at different points in time in the case where the data bus lines have different line lengths. During a time duration of 400 picoseconds, which corresponds to the data bit duration of a data transmission signal with a data transmission rate of 2.5 gigabits per second, the distance covered by the data signal at a propagation speed of 100 000 km per second is about 4 cm. Given a line length on the circuit board of 10–20 cm, for example, a plurality of data bits are simultaneously situated on a data transmission line, and propagate on the data transmission conductor track. Given data transmission rates of 2–3 gigabits per conductor track, for example, the different conductor track length can therefore bring about propagation time differences which are of the order of magnitude of the data bit duration of a transmitted data bit. This can have the effect that data transmitted in parallel via different conductor tracks of a data bus are shifted relative to one another.
FIG. 2 shows a receiving stage of an integrated circuit according to the prior art. As can be discerned from FIG. 2, ideally all the input data present on the data bus lines are accepted by the integrated circuit with a single clock signal for data processing, said clock signal being generated by a clock generator. If all the data transmission lines have the same length, only one signal delay occurs on the respective conductor track. In this case, said signal delay is of the same magnitude for all the data transmission lines. In this case, all the data transmission signals are received by the integrated circuit exactly as they were transmitted by a transmitting device. However, if there are considerable differences in the line length of the different data transmission lines, then data transmission bits belonging to different clock cycles are accepted at the inputs of the receiving stage. Compensation of the propagation time differences by taking them into account during the data processing is only possible if the propagation time differences of the different conductor tracks are known fully during the production of the integrated circuit. Moreover, a compensation is always associated with a considerable additional outlay on circuitry within the integrated circuit.
The problem brought about by the different signal propagation times is aggravated the more signals are transmitted in parallel via a bus, particularly when signals have to be applied to different housing sides of the integrated circuit, as is illustrated in FIG. 3. In the case of the arrangement illustrated in FIG. 3, drastic propagation time differences arise between the lines of the bus B, but also between the buses A and B. A simple read-in of the data present in parallel by the integrated circuit IC is eventually impossible in this case.
This becomes even clearer in FIG. 4. FIG. 4 shows merely four data lines, for simplification, namely three data lines of the data bus B and one data line of the data bus A. Since the propagation time of a transmitted data signal is directly proportional to the line length of the associated data bus line, at high data transmission rates the different line lengths of the data bus lines lead to propagation time differences which are of the order of magnitude of or greater than the time duration of a transmitted data bit. By way of example, a signal of 2.5 gigabit per second has a bit duration of 400 picoseconds. Given an assumed propagation speed of approximately 10 cm/ns, a data information bit propagates by approximately 4 cm within its bit duration. If there are different line lengths, then the individual bits reach different widths of the integrated circuit. Such propagation time differences lead to data values read in incorrectly by the integrated circuit and thus to an erroneous data processing.
In order to compensate for such propagation time difference, therefore, meander-shaped arcs have previously been inserted into the data transmission lines so as to compensate for the propagation time differences. In this case, the longest signal line in the layout determines the required propagation time compensation. The shorter the data signal line in the layout, the higher the number of meander-shaped arcs inserted for increasing the data line length. The increased data line length effects compensation of the propagation time difference with respect to the longer data signal lines. As shown in the example of FIG. 4, the meander-shaped arcs include one or more angled bends to increase the data line length for compensating for propagation time differences.
The meander-shaped course of the data signal lines leads to a considerably more complex layout of the data bus lines on the circuit board or the line card. The area available on the circuit board is very limited in many applications, so that the meander-shaped arc can be accommodated on said area only with great difficulty or not at all. Furthermore, the meander-shaped arcs lead to undesired inductances, in particular at very high data transmission rates.